Add Jtag Port

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The same page also contains the [http://www.genbako.com/jtag/kuro-jtagcable.png schematics], some pictures of the assembled jtag cable and software needed. This cable can be used without adding the additional components.
The same page also contains the [http://www.genbako.com/jtag/kuro-jtagcable.png schematics], some pictures of the assembled jtag cable and software needed. This cable can be used without adding the additional components.
 +
 +
According to http://www.abatron.ch/Files/ManAccessCOP-2000C.pdf the following pins are used for a PPC COP/JTAG interface:
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{|
 +
|- bgcolor=#CCCCCC
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|TDO
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|1
 +
|
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|2
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|QACK
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|- bgcolor=#CCCCCC
 +
 +
|TDI
 +
|3
 +
|
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|4
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|TRST (Neg)
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|- bgcolor=#CCCCCC
 +
|HALTED
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|5
 +
|
 +
|6
 +
|Vcc Target
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|- bgcolor=#CCCCCC
 +
|TCK
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|7
 +
|
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|8
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|NC (RxD)
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|- bgcolor=#CCCCCC
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|TMS
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|9
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|
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|10
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|NC (TxD)
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|- bgcolor=#CCCCCC
 +
|SRESET (Neg)
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|11
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|
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|12
 +
|Gnd
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|- bgcolor=#CCCCCC
 +
|HRESET (Neg)
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|13
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|
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|14
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|NC (key)
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|- bgcolor=#CCCCCC
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|CKSTP_OUT
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|15
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|
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|16
 +
|Gnd
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|}
 +
 +
Pin Name      Description
 +
  1  TDO        JTAG Test Data Out
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  2  QACK      ??
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  3  TDI        JTAG Test Data In
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  4  TRST      JTAG Test Reset
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  5  HALTED    ??
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  6  Vcc Target 1.8 – 5.0V:
 +
                This is the target reference voltage. It indicates that the target has power and it is also used
 +
                to create the logic-level reference for the input comparators. It also controls the output logic
 +
                levels to the target. It is normally fed from Vdd I/O on the target board.
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                3.0 – 5.0V:
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                This input is used to detect if the target is powered up. If there is a current
 +
                limiting resistor between this pin and the target Vdd, it should be 100 Ohm or less.
 +
  7  TCK        JTAG Test Clock
 +
  8  <reseved>
 +
  9  TMS        JTAG Test Mode Select
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10  <reseved>
 +
11  SRESET    Soft-Reset
 +
12  GROUND    System Ground
 +
13  HRESET    Hard-Reset
 +
14  <reseved>
 +
15  CKSTP_OUT  ??
 +
16  GROUND    System Ground
[[Category:Hardware]]
[[Category:Hardware]]
[[Category:HowTo]]
[[Category:HowTo]]

Revision as of 14:08, 31 May 2006

This document is a work in progress. It explains how to fit the internal on-chip debug (OCD) port on a Linkstation, Kuro-Box or Kuro-Box/HG to a PC interface.

Cable required: msp430-jtag.jpg

Contents

OCD connector

The internal OCD port uses an electrical standard known as JTAG/COP. The signals have to be buffered to protect the hardware from damage and we use a JTAG wiggler to do this.

Those with some electrical experience could build their own circuit, but most will opt for ordering one.

Schematics and Software to build your own

http://hri.sourceforge.net/tools/

Buy one

Commercial The Macraigor Wiggler seems to be the cheapest at $150.

Hobby Could the 20-pin Olimex ARM-JTAG be modified to work with Kuro-Box? $20.

Locate the pads

The pads are labelled CN5 and can be seen just above the serial level converter (where the yellow, orange, and red wires start to split) in this photo

Connector Pin-outs

In order to use this port, you should add the 10K series VIO resistor R67 and a 4-way 1K resistor pack at RA11. It may be possible to use some functionality without these components.

If you know which set of pin-outs that LinkStation/Kuro-Box uses, please update this page with the details.

According to Baulab the following pins are identified

TDO 1 2 ?
TDI 3 4 ?
? 5 6 ?
TCK 7 8 ?
TMS 9 10 ?
? 11 12 ?
Vcc 13 14 ?
? 15 16 Gnd


The same page also contains the schematics, some pictures of the assembled jtag cable and software needed. This cable can be used without adding the additional components.

According to http://www.abatron.ch/Files/ManAccessCOP-2000C.pdf the following pins are used for a PPC COP/JTAG interface:

TDO 1 2 QACK
TDI 3 4 TRST (Neg)
HALTED 5 6 Vcc Target
TCK 7 8 NC (RxD)
TMS 9 10 NC (TxD)
SRESET (Neg) 11 12 Gnd
HRESET (Neg) 13 14 NC (key)
CKSTP_OUT 15 16 Gnd 
Pin Name       Description
 1  TDO        JTAG Test Data Out
 2  QACK       ??
 3  TDI        JTAG Test Data In
 4  TRST       JTAG Test Reset
 5  HALTED     ??
 6  Vcc Target 1.8 – 5.0V:
               This is the target reference voltage. It indicates that the target has power and it is also used
               to create the logic-level reference for the input comparators. It also controls the output logic
               levels to the target. It is normally fed from Vdd I/O on the target board.
               3.0 – 5.0V:
               This input is used to detect if the target is powered up. If there is a current
               limiting resistor between this pin and the target Vdd, it should be 100 Ohm or less.
 7  TCK        JTAG Test Clock
 8  <reseved>
 9  TMS        JTAG Test Mode Select
10  <reseved>
11  SRESET     Soft-Reset
12  GROUND     System Ground
13  HRESET     Hard-Reset
14  <reseved>
15  CKSTP_OUT  ??
16  GROUND     System Ground
Retrieved from "http://buffalo.nas-central.org/wiki/Add_Jtag_Port"
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