Add Jtag Port
This document is a work in progress. It explains how to fit the internal on-chip debug (OCD) port on a Linkstation, Kuro-Box or Kuro-Box/HG to a PC interface.
The internal OCD port uses an electrical standard known as JTAG/COP. The signals have to be buffered to protect the hardware from damage and we use a JTAG wiggler to do this.
Those with some electrical experience could build their own circuit, but most will opt for ordering one.
Schematics and Software to build your own
Commercial The Macraigor Wiggler seems to be the cheapest at $150.
Hobby Could the 20-pin Olimex ARM-JTAG be modified to work with Kuro-Box? $20.
Locate the pads
The pads are labelled CN5 and can be seen just above the serial level converter (where the yellow, orange, and red wires start to split) in this photo
In order to use this port, you should add the 10K series VIO resistor R67 and a 4-way 1K resistor pack at RA11. It may be possible to use some functionality without these components.
If you know which set of pin-outs that LinkStation/Kuro-Box uses, please update this page with the details.
According to Baulab the following pins are identified
The same page also contains the schematics, some pictures of the assembled jtag cable and software needed. This cable can be used without adding the additional components.
According to http://www.abatron.ch/Files/ManAccessCOP-2000C.pdf and http://www.freescale.com/files/soft_dev_tools/doc/user_guide/CWH-UTP-UG.pdf the following pins are used for a PPC COP/JTAG interface:
|SRST (Neg)||11||12||Gnd (??)|
|HRST (Neg)||13||14||NC (key)|
Pin Name Description 1 TDO JTAG Test Data Out 2 QACK Not Needed 3 TDI JTAG Test Data In 4 TRST JTAG Test Reset 5 HALTED Not Needed 6 Vcc Target 1.8 – 5.0V: This is the target reference voltage. It indicates that the target has power and it is also used to create the logic-level reference for the input comparators. It also controls the output logic levels to the target. It is normally fed from Vdd I/O on the target board. 3.0 – 5.0V: This input is used to detect if the target is powered up. If there is a current limiting resistor between this pin and the target Vdd, it should be 100 Ohm or less. 7 TCK JTAG Test Clock 8 CKSI Not Connected ?? 9 TMS JTAG Test Mode Select 10 <reseved> 11 SRESET Soft-Reset 12 GROUND System Ground 13 HRESET Hard-Reset 14 <reseved> 15 CKSO Not Connected on the 8421 16 GROUND System Ground