Difference between revisions of "Category:JTAG"

From NAS-Central Buffalo - The Linkstation Wiki
Jump to: navigation, search
m (New page: A JTAG interface is a special four/five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines daisy-chained toge...)
 
m
Line 1: Line 1:
 
 
A [[w:JTAG|JTAG]] interface is a special four/five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines [[w:daisy-chain|daisy-chain]]ed together, and a [[w:test probe|test probe]] need only connect to a single "JTAG port" to have access to all chips on a [[w:circuit board|circuit board]]. The connector pins are
 
A [[w:JTAG|JTAG]] interface is a special four/five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines [[w:daisy-chain|daisy-chain]]ed together, and a [[w:test probe|test probe]] need only connect to a single "JTAG port" to have access to all chips on a [[w:circuit board|circuit board]]. The connector pins are
 
#TDI (Test Data In)
 
#TDI (Test Data In)
Line 9: Line 8:
  
 
http://upload.wikimedia.org/wikipedia/commons/thumb/c/c9/Jtag_chain.svg/300px-Jtag_chain.svg.png
 
http://upload.wikimedia.org/wikipedia/commons/thumb/c/c9/Jtag_chain.svg/300px-Jtag_chain.svg.png
 +
{{Category:Disambig}}

Revision as of 17:48, 18 July 2007

A JTAG interface is a special four/five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines daisy-chained together, and a test probe need only connect to a single "JTAG port" to have access to all chips on a circuit board. The connector pins are

  1. TDI (Test Data In)
  2. TDO (Test Data Out)
  3. TCK (Test Clock)
  4. TMS (Test Mode Select)
  5. TRST (Test ReSeT) optional.


300px-Jtag_chain.svg.png Category:Disambig