Difference between revisions of "Information/HGOverview"

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{{Template:Articles}}
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{{Template:Articles|Linkstation Variants|HG|Hardware}}
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__NOTOC__
 
==  HD-HGLAN PowerPC (HG) ==
 
==  HD-HGLAN PowerPC (HG) ==
[[Image:HD-H(G).jpg|frame|right]]
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<table align=right><tr><td>
 +
http://www.buffalotech.com/images/Gigabit.gif
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</td></tr><tr><td>[[Image:HD-H(G).jpg]]
 +
</td></tr></table>
 
:{| style="background:#DDDDDD; color:black"
 
:{| style="background:#DDDDDD; color:black"
 
|- style="background:#BBBBBB; color:green"
 
|- style="background:#BBBBBB; color:green"
 
|
 
|
 
 
| '''HD-HGLAN PowerPC (HG)'''
 
| '''HD-HGLAN PowerPC (HG)'''
 
|-
 
|-
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| 128MB ELPIDA DS2516APTA-75 SDRAM
 
| 128MB ELPIDA DS2516APTA-75 SDRAM
 
|-
 
|-
| '''Flash ROM'''
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| [[Information/HGFlashROM|'''Flash ROM''']]
| [http://www.macronix.com/index.html 4MB ST M29W320DT HG001]
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| [http://www.macronix.com/index.html 4MB ST M29W320DT HG001] or [http://www.ortodoxism.ro/datasheets/stmicroelectronics/8730.pdf ST M29DW324DT] or ST M29W324DB
|-
+
|-  
 
| '''USB'''
 
| '''USB'''
 
| [http://www.necel.com/usb/en/product/upd720101.html 2 type A(rear - /dev/usb/lp0, front - /dev/usb/lp1) - NEC D720101GJ]
 
| [http://www.necel.com/usb/en/product/upd720101.html 2 type A(rear - /dev/usb/lp0, front - /dev/usb/lp1) - NEC D720101GJ]
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| 1.x
 
| 1.x
 
|-
 
|-
| '''AVR'''
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| '''[[:AVR|AVR]]'''
 
| [http://www.atmel.com/products/AVR/overview.asp AT90S2313-4SC]
 
| [http://www.atmel.com/products/AVR/overview.asp AT90S2313-4SC]
 
|-  
 
|-  
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| [[Information/HGFilesystem|powerpc-hdhglan Filesystem contents]]  
 
| [[Information/HGFilesystem|powerpc-hdhglan Filesystem contents]]  
 
|-
 
|-
| '''Watchdog Timer'''  
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| '''Serial Access'''  
| [[Information/HGWatchdogTimer|powerpc-hdhglan Watchdog Timer Overview]]
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| [[Add_a_Serial_port_to_the_PowerPC_Linkstation|Add_a_Serial_port_to_the_PowerPC_Linkstation]]
 
|-
 
|-
 
|}
 
|}
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Some of this information courtesy of http://www.yamasita.jp/linkstation.en/index.html.
 
Some of this information courtesy of http://www.yamasita.jp/linkstation.en/index.html.
  
 
+
==Main Board==
 
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{{MPC8241}}
The following information is taken from http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8241. The [http://www.freescale.com/files/32bit/doc/data_sheet/MPC8241EC.pdf MPC8241 hardware specification data sheet] is a highly technical but excellent read.
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{{Periphery and Power Supply}}
 
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==Software==
The MPC8241 Integrated Host Processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of integration, reducing chip count from five discrete chips to one, thereby significantly reducing system component cost. High integration results in a simplified board design, less power consumption and a faster-time-to-market solution. This cost-effective, general purpose integrated processor targets systems using PCI interfaces in networking infrastructure, telecommunications, and other embedded markets. It can be used for control processing in applications such as routers, switches, network storage applications and image display systems.
+
{{Warning| You should check if you have a [[Non Flashable HD-HG300]] before trying to flash an HG with [[FreeLink]] or [[OpenLink]]}}
 
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* Stock Firmware - 1.x series
* 166-266 MHz MPC603e PowerPC processor core
+
** [http://www.buffalotech.com/downloads/HD_HGLAN_142.zip 1.42 build 2005/09/??] is the latest firmware from [http://www.buffalotech.com/support/downloads-product.php?productid=107 Buffalo North America]. Some HG-HLAN's come with version [http://downloads.nas-central.org/stock_firmware/hd-hglan_161.zip 1.61 build 2006/05/29], which is different than the [http://www2.melcoinc.co.jp/pub/hd/hglan161.exe 1.61 build 2006/04/28] firmware from [http://buffalo.jp/download/driver/hd/hd-hglan.html Buffalo Japan]) <!-- You can check the build date by looking in /etc/linkstation_release on the linkstation. If anyone knows why Buffalo NA does not show version 1.61, please post it here. -->
* 32-bit PCI interface operating at up to 66 MHz
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* [[OpenLink]] available
* Memory controller offering SDRAM support up to 133 MHz operation, support up to 2 GB
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* [[FreeLink]] available
* General Purpose I/O and ROM Interface Support
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* Two-channel DMA controller that supports chaining
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* Messaging unit with I'^2^'O messaging support capability
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* Industry-standard I'^2^'C interface
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* Programmable interrupt controller with multiple timers and counters
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* 16550 compatible DUART
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* MPC603e processor core
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** High-performance, superscalar PowerPC processor core
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** Floating-point unit, integer, load/store, system register and branch processing unit
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** 16K instruction cache, 16K data cache
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** Lockable portion of L1 cache
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** Dynamic power management
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** Software-compatible with PowerPC processors
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* Memory interface
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** 133 MHz memory bus capability
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** Programmable timing EDO DRAM or SDRAM
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** High-bandwidth bus (32/64-bit data bus) to DRAM
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** Supports one to eight banks of 16-, 64-, 128, 256 or 512Mbit DRAM
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** Supports 1 Mbyte to 2 Gbyte DRAM memory
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** Contiguous memory mapping
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** 272 Mbytes of ROM space
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** 8-bit, 16-bit, 32-bit, or 64-bit ROM
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** Supports bus-width writes to flash
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** Read-modify-write parity support (selectable)
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** ECC support (selectable)
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** SDRAM, DRAM buffer data-path
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** Error injection/capture on data path
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** LVTTL compatible
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** PortX: 8-, 16-, 32- or 64-bit general-purpose I/O port uses ROM controller interface with address strobe
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* 32-bit PCI interface operating up to 66 MHz
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** PCI 2.2 compatible
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** PCI 5.0 V tolerant
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** Support for PCI locked accesses to memory
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** Support for accesses to all PCI address spaces
+
** Selectable big- or little-endian operation
+
** Store gathering of processor-to-PCI writes and PCI-to-memory writes
+
** Memory prefetching of PCI read accesses
+
** Parity support (selectable)
+
** Selectable hardware-enforced coherency
+
** PCI bus arbitration unit (5 request/grant pairs
+
* PCI agent mode capability
+
** Address Translation Unit (ATU)
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** Run time register access
+
** PCI configuration register access
+
* Two-channel integrated DMA controller
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** Supports direct or chaining modes
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** Scatter gather
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** Interrupt on completed segment, chain, and error
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** Local to local memory
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** PCI to PCI memory
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** PCI to local memory
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** Local to PCI memory
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* Message Unit
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** (I'^2^'O) Intelligent Input/Output Message Controller
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** Two door-bell registers
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** Inbound and outbound messaging registers
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* (I'^2^'C) Inter-Integrated Circuit Controller
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** Full master/slave support
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* Embedded programmable interrupt controller (EPIC)
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** Five hardware interrupts (IRQs) or 16 serial interrupts
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** Four programmable timers
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* Integrated PCI bus and SDRAM clock generation
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* Programmable memory and PCI bus drivers
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* Debug Features
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** Watchpoint monitor
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** Memory attribute and PCI attribute signals
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** JTAG/COP - Common On-board Processor for in-circuit hardware debugging
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* Dual UART
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** 16550 Compatible
+
 
+
 
+
[[Category:Linkstation Variants]]
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[[Category:HG]]
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[[Category:Hardware]]
+

Latest revision as of 17:30, 4 January 2009


HD-HGLAN PowerPC (HG)

Gigabit.gif

HD-H(G).jpg
HD-HGLAN PowerPC (HG)
CPU 266Mhz Freescale MPC8241 with MPC603e Motorola PowerPC core.
RAM 128MB ELPIDA DS2516APTA-75 SDRAM
Flash ROM 4MB ST M29W320DT HG001 or ST M29DW324DT or ST M29W324DB
USB 2 type A(rear - /dev/usb/lp0, front - /dev/usb/lp1) - NEC D720101GJ
NIC 10/100/1000Mb Realtek RTL8110S-32 PCI ethernet controller
IDE Controller Silc0680acl144 OR IT8211 PCI IDE disk controller
Stock Firmware 1.x
AVR AT90S2313-4SC
AVR Analysis powerpc-hdhglan AVR Analysis
Benchmarks powerpc-hdhglan Benchmarks
Bootloader powerpc-hdhglan Boot Loader Overview
Flash ROM powerpc-hdhglan Flash ROM Analysis
Hardware powerpc-hdhglan Overview
Kernel powerpc-hdhglan Kernel
LED powerpc-hdhglan LED Analysis
Software powerpc-hdhglan Filesystem contents
Serial Access Add_a_Serial_port_to_the_PowerPC_Linkstation

Some of this information courtesy of http://www.yamasita.jp/linkstation.en/index.html.

Main Board

MPC8241 : Integrated Host Processor

freescale_logo.gif

The following information is taken from: MPC8241. The MPC8241 hardware specification data sheet is a highly technical but excellent read.

BUILT_ON_POWER.gif

The MPC8241 Integrated Host Processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of integration, reducing chip count from five discrete chips to one, thereby significantly reducing system component cost. High integration results in a simplified board design, less power consumption and a faster-time-to-market solution. This cost-effective, general purpose integrated processor targets systems using PCI interfaces in networking infrastructure, telecommunications, and other embedded markets. It can be used for control processing in applications such as routers, switches, network storage applications and image display systems.


MPC8241 Features

  • 166-266 MHz RISC processor core
  • 32-bit PCI interface operating at up to 66 MHz
  • Memory controller offering SDRAM support up to 133 MHz operation, support up to 2 GB
  • General Purpose I/O and ROM Interface Support
  • Two-channel DMA controller that supports chaining
  • Messaging unit with I2O messaging support capability
  • Industry-standard I2C interface
  • Programmable interrupt controller with multiple timers and counters
  • 16550 compatible DUART

Typical Applications

  • Wireless LAN
  • Routers/Switches
  • Multi-channel modems
  • Network storage
  • Image display systems
  • Enterprise I/O processor
  • Internet access device (IAD)
  • Disk controller for RAID systems
  • Copier/printer board control
  • Embedded Computing

Processor Core and On-Chip Peripheral Logic Features

  • MPC603e processor core
    • High-performance, superscalar processor core built on Power Architecture technology
    • Floating-point unit, integer, load/store, system register and branch processing unit
    • 16K instruction cache, 16K data cache
    • Lockable portion of L1 cache
    • Dynamic power management
    • Software-compatible with processors built on Power Architecture technology

On-Chip Peripheral Logic

  • Memory interface
    • 133 MHz memory bus capability
    • Programmable timing EDO DRAM or SDRAM
    • High-bandwidth bus (32/64-bit data bus) to DRAM
    • Supports one to eight banks of 16-, 64-, 128, 256 or 512Mbit DRAM
    • Supports 1 Mbyte to 2 Gbyte DRAM memory
    • Contiguous memory mapping
    • 272 Mbytes of ROM space
    • 8-bit, 16-bit, 32-bit, or 64-bit ROM
    • Supports bus-width writes to flash
    • Read-modify-write parity support (selectable)
    • ECC support (selectable)
    • SDRAM, DRAM buffer data-path
    • Error injection/capture on data path
    • LVTTL compatible
    • PortX: 8-, 16-, 32- or 64-bit general-purpose I/O port uses ROM controller interface with address strobe
  • 32-bit PCI interface operating up to 66 MHz
    • PCI 2.2 compatible
    • PCI 5.0 V tolerant
    • Support for PCI locked accesses to memory
    • Support for accesses to all PCI address spaces
    • Selectable big- or little-endian operation
    • Store gathering of processor-to-PCI writes and PCI-to-memory writes
    • Memory prefetching of PCI read accesses
    • Parity support (selectable)
    • Selectable hardware-enforced coherency
    • PCI bus arbitration unit (5 request/grant pairs
  • PCI agent mode capability
    • Address Translation Unit (ATU)
    • Run time register access
    • PCI configuration register access
  • Two-channel integrated DMA controller
    • Supports direct or chaining modes
    • Scatter gather
    • Interrupt on completed segment, chain, and error
    • Local to local memory
    • PCI to PCI memory
    • PCI to local memory
    • Local to PCI memory
  • Message Unit
    • (I2O) Intelligent Input/Output Message Controller
    • Two door-bell registers
    • Inbound and outbound messaging registers
  • (I2C) Inter-Integrated Circuit Controller
    • Full master/slave support
  • Embedded programmable interrupt controller (EPIC)
    • Five hardware interrupts (IRQs) or 16 serial interupts
    • Four programmable timers
  • Integrated PCI bus and SDRAM clock generation
  • Programmable memory and PCI bus drivers
  • Debug Features
    • Watchpoint monitor
    • Memory attribute and PCI attribute signals
    • JTAG/COP - Common On-board Processor for in-circuit hardware debugging
  • Dual UART
    • 16550 Compatible

Periphery

IDE 3.5" Disk

  • LS120: Samsung SP1203N / Western Digital WDC WD1200BB-00GUC0
  • LS160: Western Digital WD1600
  • LS250: Samsung SP2514N or V120CE(HA250JC) / Western Digital WD2500BB-22GUC0
  • LS300: Western Digital WD3200JB-00KFA0

Power Supply

  • 25W Univive Co., Ltd. "open frame" dual voltage power supply, from the UOP25D/325D series ([1], [2]). The power supply is actually a "brick" power supply without the usual plastic case. The UOP25D/325D series comes in different variations. The differences are the input voltage ranges, and the maximum output current and output voltage stability. 5V ±5%, 0.1A - 2A and 12V ±6%, 0.1A - 1.5A are typical output values.

Software

Nuvola apps important.png 
WARNING!

You should check if you have a Non Flashable HD-HG300 before trying to flash an HG with FreeLink or OpenLink