Information/HGOverview

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HD-HGLAN PowerPC (HG)

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HD-HGLAN PowerPC (HG)
CPU 266Mhz Freescale MPC8241 with MPC603e Motorola PowerPC core.
RAM 128MB ELPIDA DS2516APTA-75 SDRAM
Flash ROM 4MB ST M29W320DT HG001
USB 2 type A(rear - /dev/usb/lp0, front - /dev/usb/lp1) - NEC D720101GJ
NIC 10/100/1000Mb Realtek RTL8110S-32 PCI ethernet controller
IDE Controller Silc0680acl144 OR IT8211 PCI IDE disk controller
Stock Firmware 1.x
AVR AT90S2313-4SC
AVR Analysis powerpc-hdhglan AVR Analysis
Benchmarks powerpc-hdhglan Benchmarks
Bootloader powerpc-hdhglan Boot Loader Overview
Flash ROM powerpc-hdhglan Flash ROM Analysis
Hardware powerpc-hdhglan Overview
Kernel powerpc-hdhglan Kernel
LED powerpc-hdhglan LED Analysis
Software powerpc-hdhglan Filesystem contents
Watchdog Timer powerpc-hdhglan Watchdog Timer Overview

Some of this information courtesy of http://www.yamasita.jp/linkstation.en/index.html.

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WARNING!

You should check if you have a Non Flashable HD-HG300 before trying to flash an HG with FreeLink or OpenLink



The following information is taken from http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8241. The MPC8241 hardware specification data sheet is a highly technical but excellent read.

The MPC8241 Integrated Host Processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of integration, reducing chip count from five discrete chips to one, thereby significantly reducing system component cost. High integration results in a simplified board design, less power consumption and a faster-time-to-market solution. This cost-effective, general purpose integrated processor targets systems using PCI interfaces in networking infrastructure, telecommunications, and other embedded markets. It can be used for control processing in applications such as routers, switches, network storage applications and image display systems.

  • 166-266 MHz MPC603e PowerPC processor core
  • 32-bit PCI interface operating at up to 66 MHz
  • Memory controller offering SDRAM support up to 133 MHz operation, support up to 2 GB
  • General Purpose I/O and ROM Interface Support
  • Two-channel DMA controller that supports chaining
  • Messaging unit with I'^2^'O messaging support capability
  • Industry-standard I'^2^'C interface
  • Programmable interrupt controller with multiple timers and counters
  • 16550 compatible DUART
  • MPC603e processor core
    • High-performance, superscalar PowerPC processor core
    • Floating-point unit, integer, load/store, system register and branch processing unit
    • 16K instruction cache, 16K data cache
    • Lockable portion of L1 cache
    • Dynamic power management
    • Software-compatible with PowerPC processors
  • Memory interface
    • 133 MHz memory bus capability
    • Programmable timing EDO DRAM or SDRAM
    • High-bandwidth bus (32/64-bit data bus) to DRAM
    • Supports one to eight banks of 16-, 64-, 128, 256 or 512Mbit DRAM
    • Supports 1 Mbyte to 2 Gbyte DRAM memory
    • Contiguous memory mapping
    • 272 Mbytes of ROM space
    • 8-bit, 16-bit, 32-bit, or 64-bit ROM
    • Supports bus-width writes to flash
    • Read-modify-write parity support (selectable)
    • ECC support (selectable)
    • SDRAM, DRAM buffer data-path
    • Error injection/capture on data path
    • LVTTL compatible
    • PortX: 8-, 16-, 32- or 64-bit general-purpose I/O port uses ROM controller interface with address strobe
  • 32-bit PCI interface operating up to 66 MHz
    • PCI 2.2 compatible
    • PCI 5.0 V tolerant
    • Support for PCI locked accesses to memory
    • Support for accesses to all PCI address spaces
    • Selectable big- or little-endian operation
    • Store gathering of processor-to-PCI writes and PCI-to-memory writes
    • Memory prefetching of PCI read accesses
    • Parity support (selectable)
    • Selectable hardware-enforced coherency
    • PCI bus arbitration unit (5 request/grant pairs
  • PCI agent mode capability
    • Address Translation Unit (ATU)
    • Run time register access
    • PCI configuration register access
  • Two-channel integrated DMA controller
    • Supports direct or chaining modes
    • Scatter gather
    • Interrupt on completed segment, chain, and error
    • Local to local memory
    • PCI to PCI memory
    • PCI to local memory
    • Local to PCI memory
  • Message Unit
    • (I'^2^'O) Intelligent Input/Output Message Controller
    • Two door-bell registers
    • Inbound and outbound messaging registers
  • (I'^2^'C) Inter-Integrated Circuit Controller
    • Full master/slave support
  • Embedded programmable interrupt controller (EPIC)
    • Five hardware interrupts (IRQs) or 16 serial interrupts
    • Four programmable timers
  • Integrated PCI bus and SDRAM clock generation
  • Programmable memory and PCI bus drivers
  • Debug Features
    • Watchpoint monitor
    • Memory attribute and PCI attribute signals
    • JTAG/COP - Common On-board Processor for in-circuit hardware debugging
  • Dual UART
    • 16550 Compatible